{"product_id":"ap3101-triconex-tricon-tmr-main-processor-module","title":"AP3101 | Triconex | Tricon TMR Main Processor Module","description":"\u003ch2\u003e\u003cstrong\u003eProduct Overview\u003c\/strong\u003e\u003c\/h2\u003e\n\u003cp\u003eThe\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003eTriconex AP3101\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eserves as the primary computational engine for the Tricon Triple Modular Redundancy (TMR) safety system. This high-performance Main Processor module executes the user’s control applications, manages complex I\/O signal processing, and maintains system synchronization across triplicated channels. By utilizing dual 32-bit Motorola PowerPC architecture, it provides the deterministic execution required for SIL-3 safety loops in oil, gas, and power generation facilities. We supply this module as\u003cspan\u003e \u003c\/span\u003e\u003cstrong\u003e100% Brand New and Original factory-sealed equipment\u003c\/strong\u003e.\u003c\/p\u003e\n\u003ch2\u003e\u003cstrong\u003eTechnical Specifications\u003c\/strong\u003e\u003c\/h2\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr class=\"firstRow\"\u003e\n\u003ctd\u003e\u003cstrong\u003eComponent \/ Feature\u003c\/strong\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cstrong\u003eSpecification Details\u003c\/strong\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eApplication Processor (SX)\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eMotorola MPC860, 32-bit, 50 MHz\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eI\/O Processor (IOx)\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003eMotorola MPC860, 32-bit, 50 MHz\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eFlash PROM\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e6 MB (CRC-protected storage)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eDRAM (SX \u0026amp; IOx)\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e16 MB each (with byte parity)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eNVRAM\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e8 KB (CRC-protected variables)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eShared Memory\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e128 KB (Byte parity enabled)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eDiagnostic Bus\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e2 Mbps HDLC\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eNominal Input Voltage\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e24 VDC\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eOperational Range\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e19.2 VDC to 30.0 VDC\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003ePower Consumption\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e8 Watts (Maximum)\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e\u003cspan\u003e\u003cstrong\u003eWeight\u003c\/strong\u003e\u003c\/span\u003e\u003c\/td\u003e\n\u003ctd\u003e\u003cspan\u003e1.5 kg\u003c\/span\u003e\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch2\u003e\u003cstrong\u003eEngineering Advantages\u003c\/strong\u003e\u003c\/h2\u003e\n\u003cul class=\"list-paddingleft-2\"\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eDual-Processor Dedicated Architecture:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eThe AP3101 separates application logic from I\/O management by utilizing independent SX and IOx Motorola MPC860 processors. This division of labor prevents I\/O communication overhead from delaying critical safety logic execution, ensuring consistent 50 MHz processing speeds even during high-density I\/O traffic.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eTriple-Layer Data Protection:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eThe module employs Cyclic Redundancy Checks (CRC) for Flash and NVRAM, combined with byte parity for DRAM. This multi-layered approach identifies memory corruption immediately, preventing the execution of faulty logic that could lead to catastrophic process failure.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eDeterministic Diagnostic Bus:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eA dedicated 2 Mbps HDLC diagnostic bus transfers I\/O module health information between Main Processor channels. This isolated pathway allows the TMR system to synchronize fault data across all three MPs without consuming primary application bandwidth.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eRobust Power Regulation:\u003c\/strong\u003e\u003cspan\u003e \u003c\/span\u003eThe logic circuitry operates across a wide 24 VDC range (-15% to +20%) and tolerates up to 5% AC ripple. This electrical resilience allows the AP3101 to maintain stability during industrial power fluctuations or when operating near heavy electrical machinery.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch2\u003e\u003cstrong\u003eFAQs\u003c\/strong\u003e\u003c\/h2\u003e\n\u003cul class=\"list-paddingleft-2\"\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eHow does the AP3101 maintain safety if one processor fails?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eThe AP3101 functions within the Tricon TMR framework. If the internal diagnostics detect a failure in one channel's processor, the remaining two Main Processors continue to execute the logic and out-vote the faulty unit. This 2-out-of-3 (2oo3) voting mechanism ensures uninterrupted safety control.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eWhat is the significance of the 6 MB Flash PROM?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eThe Flash PROM stores the SX, IOx, and control application logic. Its CRC protection ensures that the software remains uncorrupted during long-term storage or under high-interference conditions, guaranteeing that the processor always boots to a valid safety state.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003cli\u003e\n\u003cp\u003e\u003cstrong\u003eDoes this module support hot-swapping?\u003c\/strong\u003e\u003c\/p\u003e\n\u003cp\u003eYes. You can replace an AP3101 module while the Tricon system remains energized and the other two Main Processors are controlling the process. The new module automatically synchronizes its memory and logic state with the active processors upon insertion.\u003c\/p\u003e\n\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"Triconex","offers":[{"title":"Default Title","offer_id":52493364265269,"sku":"9852","price":66.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0973\/7630\/5461\/files\/3664_6d5550ee-1455-4071-84a6-8846cd5c28fa.jpg?v=1774598987","url":"https:\/\/www.5gplc.com\/products\/ap3101-triconex-tricon-tmr-main-processor-module","provider":"High Five PLC Solution Limited","version":"1.0","type":"link"}